1. Field of the Invention
The present invention relates to a semiconductor memory device for storing charges as information.
2. Description of the Prior Art
FIG. 2 shows memory cell structure of a 256K dynamic RAM as an example of a conventional semiconductor memory of the aforementioned type. Referring to FIG. 2, numeral 1 indicates a P.sup.- type (first conductivity type) semiconductor substrate, numerals 2 and 3 indicate first and second gate electrodes, numeral 4 indicates a gate insulator film, numeral 5 indicates an N.sup.+ type (second conductivity type) region serving as a charge storage region, numeral 6 indicates an N.sup.+ type (second conductivity type) region serving as a bit line, numeral 7 indicates a depletion layer, numeral 8 indicates a P.sup.+ type region which is made higher in concentration than the semiconductor substrate 1 at least by one digit to expand the memory cell capacity, numeral 9 indicates a P.sup.+ type isolation (channel stop) region and numeral 10 indicates an insulator film for isolating the elements. A wiring part and a protective coat are omitted in FIG. 2.
In the conventional memory cell as shown in FIG. 2, the P.sup.+ type region 8 is formed in the periphery of the N.sup.+ type region 5 serving as the charge storage region to expand the memory cell capacity thereby to increase the critical charge amount, for preventing soft errors so that no malfunction occurs even if the charge storage region 5 collects electrons generated by radioactive rays such as alpha rays.
However, the N.sup.+ type region 6 serving as the bit line is not protected against attraction of the electrons. Further, when the wafer is inclined by several degrees (7.degree. to 8.degree.) for ion implantation to additionally implant P type impurities in the periphery of the N.sup.+ type region 6, lateral impurity diffusion is increased by collision with Si lattices, whereby a parasitic PNP transistor is operated. Thus, it has been difficult to stably drive a pass transistor.
In general, the conventional semiconductor memory device has no barrier for collecting the electrons generated by the alpha rays in the N.sup.+ type region 6, whereby soft errors are easily caused. Further, since the wafer is inclined for ion implantation, ion-implanted layers such as source and drain regions to be formed in a self-alignment manner may be blocked by masks such that ion implantation cannot be performed as designed, to cause trouble in a highly integrated circuit.